The present invention relates to a semiconductor memory and a method of manufacturing the same and, more particularly, to a DRAM (Dynamic Random Access Memory: a random access memory requiring data storage) or a DRAM embedded memory having a DRAM function, and a method of manufacturing the same.
It is increasingly demanded to maintain the cell characteristics (pause/retention) of a DRAM and increase the operating speed of a peripheral circuit at the same time. However, it is very difficult to satisfy both of these two requirements.
To increase the operating speed of a transistor in a peripheral circuit, it is possible to improve the short channel effect by decreasing the depth of source and drain layers, and increase the driving power by reducing the channel resistance. To this end, however, an impurity must be ion-implanted at low acceleration when source and drain diffusion layers are formed, thereby requiring a thin oxide film on the substrate surface.
To decrease the thickness of the oxide film on the substrate surface, the thickness of an oxide film on the side surfaces of a gate electrode must also be decreased. Unfortunately, this intensifies the gate edge electric field. Consequently, in the state in which data is stored by applying a voltage of about 0 or −0.4 [V] to the gate electrode, a GIDL (Gate Induced Drain Leakage) current by which electric charge passes through the substrate increases. This worsens the data holding characteristic.
In the conventional manufacuring method, a gate electrode side wall oxidation process is performed at once after gate electrodes are formed. Therefore, the thickness of the sidewall oxide film, the shape of an end portion of the gate electrode in contact with the substrate surface, and the thickness of the oxide film on the substrate surface in a memory cell array region are the same as those in a peripheral circuit region.
To improve the characteristics, particularly, the data holding time characteristic of a DRAM cell, it is preferable to increase the thickness of the sidewall oxide film of a transistor and increase the oxide film thickness near the end portion of the gate electrode in the memory cell array region. This is so because the GIDL current can be reduced by alleviating field concentration between the gate electrode end portion and the substrate.
In the conventional device, however, the oxide film thickness in the memory cell array region is the same as that in the peripheral circuit region. Therefore, when an impurity is ion-implanted to form source and drain layers, this ion-implantation must be performed at relatively high acceleration so that the impurity is well implanted even if a thick oxide film is present. This makes it difficult to increase the operating speed of a transistor in the peripheral circuit region by decreasing the thickness of diffusion layers of the transistor.
In contrast, if the sidewall oxide film thickness of the gate electrode is reduced to decrease the thickness of the source and drain diffusion layers of the transistor in the peripheral circuit region, the end-portion film thickness of the gate electrode of the transistor in the memory cell array region also decreases. This increases the GIDL current and deteriorates the data holding characteristic.
Examples of references disclosing the conventional semiconductor memories are as follows.
[Patent Reference 1]
Japanese Patent Laid-Open No. 2002-43549
[Patent Reference 2]
U.S. Pat. No. 6,235,574B1
In the conventional semiconductor memory as described above, the optimum conditions of the sidewall oxide film thickness of the gate electrode in the memory cell array region have a tradeoff relationship with those in the peripheral circuit region. Accordingly, it is necessary to sacrifice one of these gate electrodes or to form them under intermediate conditions. This makes it impossible to improve the holding characteristic of the memory cell and increase the operating speed of the peripheral circuit at the same time.